Mechanical stresses within a semiconductor device substrate can modulate device performance. That is, stresses within a semiconductor device are known to enhance semiconductor device characteristics. Thus, to improve the characteristics of a semiconductor device, tensile and/or compressive stresses are created in the channel of the NFETs and/or PFETs.
In order to maximize the performance of NFETs and PFETs within integrated circuit (IC) chips, the stress components should be engineered and applied differently for NFETs and PFETs as the type of stress beneficial for the performance of an NFET is generally disadvantageous for the performance of the PFET. More particularly, when a device is in tension, the performance characteristics of the NFET are enhanced while the performance characteristics of the PFET are diminished.
In known processes for implementing stresses in FETs, distinct processes and/or materials are used to create such stresses. For example, as shown in FIG. 1, it is known to grow SiGe in recesses in the substrate which are in contacted and bounded by an STI structure. According to this method, the substrate between the gate structure and the isolation region (STI) is etched to form recesses. These recesses are bounded by the STI structure and more particularly the oxide material which forms the STI structure. However, in these known methods, the SiGe material does not grow uniformly within the recesses due to its faceted profile. In fact, due to the characteristics of the SiGe and remaining structure, the SiGe has a tendency to grow faster along sidewalls of the substrate, e.g., silicon, than the oxide of the STI structure.
Due to this faceted profile, a triangular-shaped trench forms along the STI structure that extends to the bottom of the silicon recess. This trench results in serious processing problems such as, for example, junction leakage problems. More specifically, the junction leakage problem results from silicide being taken down to the bottom of the silicon recess during subsequent processing steps. Also, the trench makes it more difficult to ensure desired topography when patterning with lithographic processes. Another problem is the dependence of the performance enhancement on the spacing between devices. This dependence is due to the recess RIE loading, amongst other factors.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.